 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| SC-604 Speech And Music Processor Data sheet Features Advanced, Integrated Speech Synthesizer for High-Quality Sound Operates up to 12.32 MHz (Performs up to 12 MIPS) Slave Mode Enables Hours of Speech Using an External Processor and Memory Master Mode Allows 6.8 Minutes of Speech Onboard Supports High-Quality Synthesis Algorithms such as MX, CX, Simple CX, LX, ADPCM, and Polyphonic Music Simultaneous Speech Plus Music Capabilities Very Low-Power Operation, Ideal for Hand-Held Devices Low-Voltage Operation, Sustainable by Three (3) Batteries Reduced Power Standby Modes, Less Than 10 A in Deep-Sleep Mode 16 General-Purpose I/O Pins (in Master Mode) or 4 General-Purpose I/O Pins (in Slave Mode) Resistor-Trimmed Oscillator or 32.768-kHz Crystal Reference Oscillator Slave Interface Logic Contains 64K BytesWords Onboard ROM (2K Words Reserved) 640-Word RAM Direct Speaker Drive, 32 (PDM) One-Bit Comparator With Edge Detection Interrupt Service Serial Scan Port for In-Circuit Emulation, Monitor, and Test Available in Die Form or 64-Pin LQFP Package Description The SC-604 is a low-cost, mixed-signal processor that combines a speech synthesizer with a dedicated slave interface logic, generalpurpose I/O, onboard ROM, and direct speakerdrive in a single package. The computational unit uses a powerful new DSP that gives the SC604 unprecedented speed and computational flexibility compared with previous devices of its type. The SC-604 supports a variety of speech and audio coding algorithms, providing a range of options with respect to speech duration and sound quality. SC-691 Block Diagram 16-Bit Microprocessor 10-Bit DAC 640-words RAM TIMER 1 TIMER 2 PLLM SLAVE LOGIC 64K-Bytes ROM COMPARATOR The device consists of a micro-DSP core, embedded program and data memory, and a self-contained clock generation system. General-purpose periphery is comprised of 16 bits of partially configurable I/O. The core processor is a general-purpose 16-bit microcontroller with DSP capability. The basic core block includes a computational unit (CU), data address unit, program address unit, two timers, eight-level interrupt processor, and several system and control registers. The core processor gives the SC-604break-point capability in emulation. The processor is a Harvard type for efficient DSP algorithm execution, separating program and data memory blocks to permit simultaneous access. The ROM has a protection scheme to prevent third-party pirating. It is configured in 32K 17-bit words. The total ROM space is divided into two areas: 1) The lower 2K words are reserved by Sensory, Inc. for a built-in self-test 2) The upper 30K is for user program and data space. (c) 2002 Sensory Inc. P/N 80-0208-B 1 SC-604 Data sheet The data memory is internal static RAM. The RAM is configured in 640 17-bit words. All memories are designed to consume minimum power at a given system clock and algorithm acquisition frequency. A flexible clock generation system enables the software to control the clock over a wide frequency range. The implementation uses a phase-locked loop (PLL) circuit that drives the processor clock at a selectable frequency between the minimum and maximum achievable. Selectable frequencies for the processor clock are spaced apart in 65.536-kHz steps. The PLL clock-reference is also selectable; either a resistor-trimmed oscillator or a crystal-referenced oscillator may be used. Internal and external clock sources are controlled separately to provide different levels of power management. The periphery consists of two 8-bit-wide general-purpose I/O ports when operating in master mode, or four general-purpose I/O pins in slave mode. In the master mode, the bidirectional I/O can be configured under software control as either high-impedance inputs or as totem-pole output. They are controlled via addressable I/O registers. These features make the input port especially useful as a key-scan interface. Slave mode consists of four general-purpose I/O, four control pins, and eight bidirectional data pins. A simple one-bit comparator is also included in the periphery. The comparator is enabled by a control register, and its access is shared with two pins in one general-purpose I/O port. Rounding out the SC-604 periphery is a built-in pulse-density-modulated DAC (digital-to-analog converter) with direct speaker-drive capability. The following block diagram gives an overview of the SC-604functionality. Functional block diagram 2 P/N 80-0208-B (c) 2002 Sensory Inc. Data Sheet SC-604 Functional Description The SC-604 is a member of the SC-6x family, which is based on the SC-614 core. For specific details about the core operations, instruction sets, register definitions, port configuration, etc., consult the SC-614 User's Guide (80-0212). The SC-604 can be used as a slave synthesizer in slave mode or can operate stand-alone in master mode. The slave mode activates logic circuitry internal to the device that gives the device a dedicated slave interface. The slave or master mode is controlled by the bit 0 of the Port G (PG0). By default the device initially starts in slave mode. To change to master mode write a 0x01 to G port 0 (0x2C). To change back to slave mode write a 0x00 to port G bit 0 (0x2C). Master Mode In master mode, the slave logic circuitry is disabled and SC-604has 16 general-purpose I/Os. These 16 input/output pins are organized as 2-byte-wide ports (C and D), initialized as inputs. Each of the pins can be configured as a totem-pole output or as a high-impedance input by setting or clearing the appropriate bit in the appropriate control register (0x14, 0x1C). When configured as an output, the data driven by the output pin can be controlled by setting or clearing the appropriate bit in the appropriate data register (0x10, 0x18). Whether configured as input or as output, reading the data port reads the actual state of the pin. External interrupts can be caused by transitions on pins PD2, PD3, PD4, and PD5 in the master mode. These interrupts are supported whether the pins are programmed as inputs or outputs. Slave Mode In slave mode, the slave logic circuitry is enabled allowing the device to have a dedicated slave interface. In this mode, only four pins of port D (PD4-PD7) are available as general-purpose I/O while the remaining pins (PD0- PD3) are redefined as INRDY, OUTRDY, STROBE and R/W. These pins are used to operate the slave interface. The SC-604controls the INRDY and OUTRDY pins to let the external microcontroller know when the slave is ready to accept or transmit data. The external microcontroller controls the R/W and STROBE pins of SC-604to sequence the read/write data flow. Each read or write sequence generates an interrupt that needs to be serviced by an interrupt service routine. These interrupt service routines need to be written by the code developer. The INT3 interrupt service routine indicates that the host has completed the write sequence, and the slave should read the data from port A. The INT4 interrupt service routine indicates the host has completed the read sequence. An interrupt is not generated when a read/write is done on port G bit 0 (PG0). The slave interface consists of: 8-bit bidirectional data bus (PC0-PC7) 2 status outputs: INRDY/PD0, and OUTRDY/PD1 2 control inputs: STROBE/PD2, and R/W/PD3 4 general-purpose I/Os (PD4-PD7) Port C is used as an 8-bit bidirectional data bus. When data is to be sent to the host, it needs to be written to port C data register (0x10). When data is read from the host, it needs to be read from port A data register (0x00). Port A pins are not physically brought outside the device but are internally connected with the pins of port C. System Initialization Sequence In The Slave Mode Initialize the host processor first. The host must hold the slave RESET pin low until the slave STROBE pin can be held high by the host throughout the slave initialization process. The INRDY and OUTRDY pins are set high by the slave on the rising edge of the slave RESET pin. Slave Mode Software Initialization Write 0x00 to port A (0x00), port C (0x10), port D (0x18) data registers. Configure the port C (PC0-PC7), port D0, and port D1 as output ports. (Write 0xFF to port C (0x14) and 0x03 to port D (0x1C) control registers) (c) 2002 Sensory Inc. P/N 80-0208-B 3 SC-604 Data sheet Configure port A (PA0-PA7), PORT D2, and port D3 as input ports (default at reset). Write 0x00 to port A (0x04) and 0x03 to port D (0x1C) control registers. After the slave completes its initialization, the slave needs to inform the host that it is ready to read or write data. Note: the default mode for the MSP50C604 is the slave mode. The MSP50C604 can be set to master mode by writing a 1 to port G bit 0. This is an internal bit that is not available on the MSP50C604 external pins. Note: the initialization sequence given previously is a specific requirement for setting up the MSP50C604 in slave mode. For the basic initialization requirements of the device, please refer to the MSP50C614 user's guide (SPSU014). Write To Slave In The Slave Mode The slave indicates it is ready to receive data from the host by dropping INRDY low. This is done by writing low-high-low to port D (0x18) bit 0 (PD0). On the falling edge of the internal PD0 pulse, INRDY toggles low, notifying the host that the slave is ready to receive data. The host writes data to the slave by setting R/W low and then pulsing the STROBE high-low-high. The slave latches the data on the rising edge of the STROBE pulse and sets INRDY high. An INT3 interrupt is generated as INRDY goes high completing the write cycle. The latched data is read by the slave through port A (0x00) data register. Read From Slave In The Slave Mode When the slave has data for the host, it places the data in port C (0x10). The slave then indicates that the data is ready by dropping OUTRDY low. This is done by writing low-highlow to port D (0x18) bit 1 (PD1). On the falling edge of the internal PD1 pulse, OUTRDY toggles low notifying the host that the slave is ready to send data. The host responds by setting R/W high and then pulsing STROBE high-low-high. The host should latch the data before raising STROBE high. This informs the slave that the data has been written to the host. The OUTRDY is pulled high by the slave at the rising edge of STROBE. An INT4 interrupt is generated as OUTRDY goes high completing the read cycle. 4 P/N 80-0208-B (c) 2002 Sensory Inc. Data Sheet SC-604 Timing Diagram Write to Slave 1. Slave signals readiness to receive data from host. 2. Slave drops INRDY. 3. Host drops R/W to indicate a write. 4. Host drops STROBE. 5. Host places data on the bus. 6. Host raises STROBE indicating data is valid. 7. Slave raises INRDY, latching the data. 8. INT3 is triggered when INRDY rises. Read from Slave 1. Slave signals readiness to send data to host. 2. Slave drops OUTRDY. 3. Host raises R/W to indicate a read. 4. Host drops STROBE. 5. Slave places data on the bus. 6. Host raises STROBE after reading the data. 7. Slave raises OUTRDY. 8. INT4 is triggered when OUTRDY rises. Timing Constrains Write to Slave Read from Slave INRDY low to STROBE low tIS (min) = 5 ns OUTRDY low to STROBE low tOS (min) = 5 ns R/W to STROBE low tRS (min) = 75 ns R/W to STROBE low tRS (min) = 75 ns STROBE low tST (min) = 100 ns STROBE low tST (min) = 100 ns STROBE high to R/W tSR (min) = 25 ns STROBE high to R/W tSR (min) = 25 ns STROBE high to INRDY high tSI (max) = 75 ns STROBE high to OUTRDY high tSO (max) = 75 ns Data setup tS (min) = 15 ns STROBE Low to data valid tDV (max) = 90 ns Data hold tH (min) = 80 ns STROBE High to data high Z tDZ (min) = 90 ns (c) 2002 Sensory Inc. P/N 80-0208-B 5 SC-604 Data sheet Pin/Pad Assignments VSS NC NC VSS 50 49 48 47 46 45 44 43 NC NC NC NC NC NC NC NC NC NC 54 53 NC NC 52 51 64 63 62 61 60 59 58 57 56 55 36 35 VDD VDD R/W_ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VSS DACP VDD DACM VDD PD4 PD5 PD6 PD7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 1 34 STROBE_ OUTRDY_ INRDY_ TEST SC-604 (top view of the die) SCANOUT SYNC SCANCLK SCANIN RESET_ SC-604 (64-lead LQFP) 42 41 40 39 38 37 36 35 34 33 16 17 PLL OSCIN OSCOUT VSS NC VDD NC NC NC NC NC NC NC NC NC NC NC NC NC NAME PC0 - PC7 PD4 - PD7 PD0/INRDY PD1/OUTRDY_ PD2/STROBE_ PD3/R/W_ PIN NO. 39 32 43 40 6 5 4 3 PAD NO. 25 18 29 26 6 5 4 3 I/O I/O I/O I/O O I/O O I/O O I/O O I O I I I DESCRIPTION Port C general-purpose I/O (1 Byte) Port D general-purpose I/O (1 Byte) (Master) Port D general-purpose I/O (Slave) INRDY output to host (Master) Port D general-purpose I/O (Slave) OUTRDY_ output to host (Master) Port D general-purpose I/O (Slave) STROBE_ input from host (Master) Port D general-purpose I/O (Slave) Read/write input from host Scan port data input Scan port data output Scan port clock Scan port synchronization Test modes Pins PD4 and PD5 may be dedicated to the comparator function, if the comparator enable bit is set. Scan Port Control Signals SCANIN 11 SCANOUT 8 SCANCLK 10 SYNC 9 TEST 7 11 8 10 9 7 The scan port pins must be bonded out on any SC-604 production board. Reference Oscillator Signals OSCOUT 15 15 OSCIN 14 14 PLL 13 13 Digital-to-Analog Sound Output DACP 47 33 DACM 45 31 Initialization RESET_ 12 12 Power Signals V SS 16, 48, 49, 64 16, 34, 35, 36 V DD 1, 2, 31, 44, 46 1, 2, 17, 30, 32 O Resistor/crystal reference out I Resistor/crystal reference in O Phase-lock-loop filter O Digital-to-analog plus output (+) O Digital-to-analog minus output (-) I Initialization Ground Processor power (+) The VSS and VDD connections service the DAC circuitry. Their pins tend to sustain a higher current draw. A dedicated decoupling capacitor across these pins is therefore required. 6 P/N 80-0208-B (c) 2002 Sensory Inc. PC7 Data Sheet SC-604 Absolute Maximum Ratings Absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VDD (see Note 1) Supply current, IDD (see Note 2) Input voltage range, VI (see Note 1) Output voltage range, VO (see Note 1) Storage temperature range, TA -0.3 to 7 V 35 mA -0.3 to VDD + 0.3 V -0.3 to VDD + 0.3 V -30C to 125C WARNING: Stressing the SC-604 beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability. NOTES: 1. Unless otherwise noted, all voltages are measured with respect to VSS. 2. The total supply current includes the current out of all the I/O pins as well as the operating current of the device. Recommended Operating Conditions Supply voltage (with respect to VSS), VDD CPU clock rate (as programmed), f(CPU) Load resistance between DACP and DACM, R(DAC) Operating free-air temperature, TA MIN 3 64 32 0 MAX 5.2 12,320 70 UNIT V kHz C Device functionality Timing Requirements t(RESET) t1(WIDTH) t2(WIDTH) Reset_ low pulse width, while VDD is within specified limits Pulse width required prior to a negative transition at pin PD3, PD5, or PF0 PF7 Pulse width required prior to a positive transition at pin PD2 or PD4 MIN 100 2 2 MAX UNIT ns 1/FCPU 1/FCPU While these pins are being used as interrupt inputs. t(RESET) t(RESET) Figure 1: Initialization Timing Diagram t1(WIDTH (PD3, PD5, or F port)) t2(WIDTH (PD2, or PD4)) t1(WIDTH) t2(WIDTH) Figure 2: External Interrupt Pin Pulse Width Requirements t1WIDTH and t2WIDTH (c) 2002 Sensory Inc. P/N 80-0208-B 7 SC-604 Data sheet DC Electrical Characteristics, TA = 0 to 70C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Positive going threshold 2.4 VDD = 3 V V Negative going threshold 1.8 Hysteresis 0.6 Threshold changes Positive going threshold 3.3 V VDD = 5.2 V Negative going threshold 2.9 Hysteresis 0.4 VDD = 3 V 2 3 V High-level input voltage VDD = 4.5 V 3 4.5 3.5 5.2 VDD = 5.2 V VDD = 3 V 0 1 V Low-level input voltage VDD = 4.5 V 0 1.5 0 1.7 VDD = 5.2 V High-level output current per pin of I/O port VOH = 4 V -2 mA Low-level output current per pin of I/O port VOL = 0.5 V 5 mA VDD = 4.5 V High-level output DAC current VOH = 4 V -10 mA VOL = 0.5 V Low-level output DAC current 20 mA Input leakage current Excludes OSCIN 1 A Standby current RESET is low 0.05 10 A Operating current VDD = 4.5 V, FCLOCK = 12.32 MHz 15 mA VDD = 4.5 V, DAC off, ARM set, OSC disabled 0.05 10 Supply current A VDD = 4.5 V, DAC off, ARM set, OSC enabled 40 60 VDD = 4.5 V, DAC off, ARM clear, OSC enabled 60 100 Input offset voltage VDD = 4.5 V, Vref = 1 to 4.25 V 25 50 mV F port pullup resistance VDD = 5 V 70 150 K RRTO = 470 K, VDD = 4.5 V, TA = 25C, 1% 3% Trim deviation fRTO = 8.192 MHz (PLL setting = 7 Ch) RRTO = 470 K, VDD = 3.5 to 5.2 V, TA = 25C, Voltage deviation 1.5% fRTO = 8.192 MHz (PLL setting = 7 Ch) RRTO = 470 K, VDD = 4.5 V, TA = 0 to 70C, Temperature deviation 0.03 %/C fRTO = 8.192 MHz (PLL setting = 7 Ch) VDD = 4.5 V, TA = 25C, R(OSC) = 470 K at 1%, 1% Resistance deviation fRTO = 8.192 MHz (PLL setting = 7 Ch) RESET_ VIH VIL IOH IOL IOH (DAC) IOL (DAC) Ilkg I(STANDBY) IDD I(SLEEP-deep) I(SLEEP-mid) I(SLEEP-light) VIO R(PULLUP) f(RTO-trim) f(RTO-volt) f(RTO-temp) f(RTO-res) Operating current assumes all inputs are tied to either VSS or VDD with no input currents due to programmed pullup resistors. The DAC output and other outputs are open circuited. The best trim value is selected at nominal temperature and voltage but the deviation due to the trim error is ignored. Typical voltage and current measurement taken at 25C Cannot exceed 15 mA total per internal VDD pin. Port A, B share 1 internal VDD pin; Port C, D share 1 internal VDD. External Component Absolute Values PARAMETER R(RTO) RTO external resistance C(PLL) PLL external capacitance TEST CONDITIONS TA = 25C, 1% tolerance TA = 25C, 10% tolerance MIN MAX 470 3300 UNIT K pF 8 P/N 80-0208-B (c) 2002 Sensory Inc. Data Sheet SC-604 Mechanical Data LQFP 64 PLASTICQUAD FLATPACK (10x10x1.4 mm) Symbol Dimension in mm Dimension in inch Min Nom Max Min Nom Max A 1.60 0.063 A1 0.05 0.15 0.002 0.006 A2 1.35 1.40 1.45 0.053 0.055 0.057 Notes: A. B. C. All linear dimensions are in millimeters. This drawing is subject to change without notice. Falls within JEDEC MS-022 (c) 2002 Sensory Inc. P/N 80-0208-B 9 SC-604 Data sheet b 0.17 0.22 0.27 0.007 0.009 0.011 b1 0.17 0.20 0.23 0.007 0.008 0.009 c 0.09 0.20 0.004 0.008 c1 0.09 0.16 0.004 0.006 D 12.00 BSC 0.472 BSC D1 10.00 BSC 0.394 BSC E 12.00 BSC 0.472 BSC E1 10.00 BSC 0.394 BSC 0.50 BSC 0.20 BSC L 0.45 0.60 0.75 0.018 0.024 0.030 L1 1.00 REF 0.039 BSC R1 0.08 0.003 - 10 P/N 80-0208-B (c) 2002 Sensory Inc. Data Sheet R2 0.08 0.20 0.003 0.008 S 0.20 0.008 0 3.5 7 0 3.5 7 1 0 0 2 12 TYP 12 TYP 3 12 TYP 12 TYP SC-604 (c) 2002 Sensory Inc. P/N 80-0208-B 11 SC-604 Data sheet Die Bond-out Coordinates Die Size = 147.64 x 111.02 Mil Pad Size = 210 x 210 Mil Units = Metric Pad 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 64 X-Axis Min 149.00 149.00 127.40 127.40 127.40 127.40 127.30 127.40 127.30 127.30 127.30 127.45 127.30 127.30 127.30 148.00 3385.20 3472.20 3472.20 3472.20 3472.20 3472.20 3472.20 3472.20 3472.20 3472.20 3472.20 3472.20 3472.20 3450.60 3517.01 3517.01 3517.01 3516.80 3149.35 97.30 Y-Axis Min 2122.80 1961.45 1805.45 1651.45 1497.45 1343.45 1191.05 1077.95 925.45 814.15 702.85 555.50 435.50 324.20 212.90 108.10 61.50 172.75 326.75 480.75 634.75 788.75 942.75 1096.75 1250.75 1404.75 1558.75 1712.75 1866.75 2026.15 2165.85 2319.91 2473.95 2583.45 2581.75 2533.65 X-Axis Max 235.00 235.00 213.40 213.40 213.40 213.40 213.30 213.40 213.30 213.30 213.30 213.45 213.30 213.30 213.30 234.00 3471.20 3558.20 3558.20 3558.20 3558.20 3558.20 3558.20 3558.20 3558.20 3558.20 3558.20 3558.20 3558.20 3536.60 3603.01 3603.01 3603.01 3602.80 3235.35 183.30 Y- Axis Max 2208.80 2047.45 1891.45 1737.45 1583.45 1429.45 1277.05 1163.95 1011.45 900.15 788.85 641.50 521.50 410.20 298.90 194.10 147.50 258.75 412.75 566.75 720.75 874.75 1028.75 1182.75 1336.75 1490.75 1644.75 1798.75 1952.75 2112.15 2251.85 2405.91 2559.95 2669.45 2667.75 2619.65 Ordering Information Part SC-604 DIE SC-604 LQFP Ordering P/N SC604-R SC604-RL1 Shipping P/N Description 65-xxxx-x Tested, Singulated SC-604 die in waffle pack. 65-xxxx-x SC-604 64 pin 10x10x1.4mm LQFP 12 P/N 80-0208-B (c) 2002 Sensory Inc. The Interactive SpeechTM Product Line The Interactive Speech line of ICs and software was developed to "bring life to products" through advanced speech recognition and audio technology. The Interactive Speech Product Line was designed for consumer telephony products and cost-sensitive consumer electronic applications such as home electronics, personal security, and personal communication. The product line includes award-winning RSC series general-purpose microcontrollers and tools, SC series of speech microcontrollers, plus a line of easy-to-implement chips that can be pin-configured or controlled by an external host microcontroller. Sensory's software technologies run on a variety of microcontrollers and DSPs. RSC Microcontrollers and Tools The RSC product line contains low-cost 8-bit speech-optimized microcontrollers designed for use in consumer electronics. All members of the RSC family are fully integrated and include A/D, pre-amplifier, D/A, ROM, and RAM circuitry. The RSC family can perform a full range of speech/audio functions including speech recognition, speaker verification, speech and music synthesis, and voice record/playback. The family is supported by a complete suite of evaluation tools and development kits. SC Microcontrollers and Tools The SC-6x product line feature the highest quality speech synthesis ICs at the lowest data rate in the industry. The line includes a 12.32 MIPS processor for high-quality low data-rate speech compression and MIDI music synthesis, with plenty of power left over for other processor and control functions. Members of the SC-6x line can store as much as 37 minutes of speech on chip and include as much as 64 I/O pins for external interfacing. Integrating this broad range of features onto a single chip enables developers to create products with high quality, long duration speech at very competitive price points. Application Specific Standard Products (ASSPs) Voice DirectTM 364 provides inexpensive speaker-dependent speech recognition and speech synthesis. This easy-to-use, pinconfigurable chip requires no custom programming and can recognize up to 60 trained words in slave mode, and 15 words in standalone mode. Ideal for speaker-dependent command and control of household consumer products, Voice Direct* 364 is part of a complete product line that includes the IC, module, and Voice Direct 364 Speech Recognition Kit. Voice ExtremeTM simplifies the creation of fully custom speech-enabled products by offering developers the capability of programming the chip in a high-level C-like language. Program code, speech data, and even record and playback information can be stored on a single off-chip Flash memory. Based on Sensory's RSC-364 speech processor, Voice Extreme includes a highly efficient on-chip code interpreter, and is supported by a comprehensive suite of low-cost development tools. Software and Technology Voice ActivationTM micro footprint software provides advanced speech technology on a variety of microcontroller and DSP platforms. A flexible design with a broad range of technologies allows manufacturers to easily integrate speech functionality into consumer electronic products. Fluent SpeechTM small footprint software recognizes up to 50,000 words; offers Animated Speech with the ability to automate enunciation and articulation; performs text-to-speech synthesis in either male or female voices; provides noise and echo cancellation, performs Wordspotting for natural language usage; offers telephone barge-in; and provides continuous digit recognition. Important notices Reasonable efforts have been made to verify the accuracy of information contained herein, however no guarantee can be made of accuracy or applicability. Sensory reserves the right to change any specification or description contained herein. Sensory reserves the right to make changes to or to discontinue any product or service identified in this publication at any time without notice in order to improve design and supply the best possible product. Sensory does not assume responsibility for use of any circuitry other than circuitry entirely embodied in a Sensory product. Information contained herein is provided gratuitously and without liability to any user. Reasonable efforts have been made to verify the accuracy of this information but no guarantee whatsoever is given as to the accuracy or as to its applicability to particular uses. Applications described in this data sheet are for illustrative purposes only, and Sensory makes no warranties or representations that the RSC/SC series of products will be suitable for such applications. In every instance, it must be the responsibility of the user to determine the suitability of the products for each application. Sensory products are not authorized for use as critical components in life support devices or systems. Sensory conveys no license or title, either expressed or implied, under any patent, copyright, or mask work right to the RSC series of products, and Sensory makes balance between recognition and synthesis no warranties or representations that the RSC series of products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Nothing contained herein shall be construed as a recommendation to use any product in violation of existing patents or other rights of third parties. The sale of any Sensory product is subject to all Sensory Terms and Conditions of Sales and Sales Policies. (c) 2001 SENSORY, INC. ALL RIGHT RESERVED. Sensory is registered by the U.S. Patent and Trademark Office. All other trademarks or registered trademarks are the 1991 Russell Ave., Santa Clara, CA 95054 Tel: (408) 327-9000 Fax: (408) 727-4748 property of their respective owners. www.sensoryinc.com |
Price & Availability of 80-0208-B
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |